During the first day, I was given a new timetable which is this
I will state only the time I'm dismiss
Mon = 5pm
Tue = 3pm
Wed = 5pm
Thu = 3pm
Fri = 12.30pm
Pretty long huh?
and my mini project, which was pretty fast. Speaking about first day of school in fact.
Firstly I have this set in my "evidence file"
In the file I have a packet of component which is to be place in the
Veroboard. Well it's not done as you can see, and the blue thingy (variable resistor) is misplace too.
Using this Circuit Diagram or a.k.a Schematic diagram we are suppose to
Draw on this paper which is called the layout diagram.
So after drawing the layout, we use the component in the component packet and place it in the veroboard to form a circuit. Which is what you saw previously..
That's all for the day. This project is given 2 weeks to complete. Before the CHINESE NEW YEAR...
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